The trend in modern microprocessor integrated circuits is to move to higher and higher levels of integration and smaller physical structures. Much of what used to be board level circuitry and additional co-processing integrated circuits has now been moved within a single microprocessor chip. The impetus for incorporating more and more circuitry and functions within single chips are the design goals of reduced size (more functionality within a reduced footprint), more speed (higher operating clock frequency), and improved performance (processing of more functional operations in a smaller time period). Other goals may also include reduced power consumption, reduced cost, and targeted market stipulations.
As the amount of logic contained within a single integrated microprocessor grows, other engineering issues also become a concern. With multiple level metal layers and buried logic structures in the physical device (logic located on the integrated circuit that has limited accessibility both logically and physically), as well as integration levels in the millions of transistors, issues such as manufacturability, reliability, and testability become more important and also become more costly items in the overall product cycle.
Several methods have been applied to address these issues. At first the board level testability methods that incorporated observability and controllability were moved into the integrated circuit along with the board level functionality. These methods were know as Ad Hoc testability and included such methods as discrete test points, data capture registers, and other invasive circuitry. These methods were shown to be costly in area, highly inefficient for overall testability, and affected performance in a negative manner.
To become more efficient, the VLSI and microprocessor fabrication industry began to use structured testability methods such as partial scan/full scan to provide controllability and observability of internal nodes of the integrated circuits. The scan methodology is excellent for conducting overall product test using an external tester which is usually very expensive. The external tester can determine faults resulting from the silicon manufacturing process, fabrication test; and determine faults due to the dicing and packaging process, manufacturing test. The external tester does not fully address other test environments such as burn-in (determining faults that cause infant mortality due to the stresses of first applying power, voltage, current, and the effects of operating temperature, to the device under test) and self-contained diagnostic or confidence testing.
Another method used to address manufacturing test and the other test environments was Built-In-Self-Test (BIST). In its original form designs were also taken from the circuit board level environment and were implemented using conventional implementations of Linear FeedBack Shift Registers (LFSRs) to provide pseudo-random patterns to sections of integrated circuit logic wherein "pseudo-random" means that the patterns created by an LFSR are repeatable for a given starting point. Eventually, the conventional LFSR was also coupled with the use of conventional scan to allow the pattern generation process to provide information for conventional scan chains.
The problem with the existing conventional methodologies and current art is that they are aimed at conducting tests targeting manufacturing level fault coverage, which can be viewed as a replacement manufacturing test. Since this type of testing is just as easily done with an external tester, the BISTs designed like this are grossly inefficient in engineering goals such as logic or die area impact and performance impact to the functional operations. There have been many papers published concerning creating tests that have higher fault coverage by using methods such as changing seeds (initial values) and polynomials (feedback connections to a serial shift register) during testing. The result of implementing the algorithms described in the literature are pattern generators that have high register counts, many levels of multiplexors to allow many different polynomials to be installed, multiple memories to hold the seeds and polynomial values, and multiple counters to sequence and synchronize all operations of the pattern generator. A common example of this is the Built-In-Logic-Block-Observer (BILBO).
The biggest problems of conventional pattern generators and test controllers based on these structures are that they take up a lot of physical area and may not be able to run at the rated frequency of the device-under-test due to the complexity involved with fetching and installing seeds and polynomials in an LFSR. The most common Test Controller design requires a LFSR and two or more equal length counters. One counter is used to determine when the LFSR has cycled through one seed value, another counter is used to determine when the LFSR has cycled through all possible seeds, and more counters are needed if the polynomial is changed (requiring at least three registers, but usually more in order to be practical, as shown below). Polynomials and seeds are usually stored so that they can be applied in some pre-determined order. This order requires even more counters, or memory storage devices in addition to those listed above. The inclusion of a memory storage device also requires control logic to activate the memory access at the correct point in the testing sequence so that the seed or polynomial is installed at the correct time. This means that a test controller circuit based on a 16-bit PRPG LFSR will require a 16-bit counter to identify when the first seed has completed, another 16-bit counter to count when the set of seeds has completed, a 16-bit by 2.sup.N memory to store the 2.sup.N possible seed values, a 16-bit register to apply the polynomial feedback terms to the 16 shift register bits (through 16 multiplexers), a 16-bit by M memory to store the M possible polynomial values, a counter or state machine to identify when to change the polynomial, and the control logic necessary to operate the memory and install the seed and polynomial values to the various registers. This is quite a bit of logic to include within an integrated circuit just to accomplish a Built-In Self-Test.
Even more complexity is added to the above described circuit if it also must coordinate and sequence a scan architecture and LFSR based signature analyzers. This means that the PRPG LFSR must supply patterns to the scan chain or chains until they are full and then establish the mode, enable, select, or clock signals necessary to accomplish a sample cycle (just shifting data through the scan shift chains is not a sufficient test). Once the chips response to the shifted in scan state is sampled into the scan chain, the data must be processed to evaluate if any resulting data is correct or not. This is usually done by compressing the data into a conventional signature analyzer or data compression circuit. Counters must be provided to indicate to the scan architecture when it is the proper time to conduct the sample cycle, counters must be provided to enable the data compression device (so that it does not sample random or indeterminate data, such as the default power-up state, that can occur before the first PRPG pattern fills the scan chain with known deterministic values), and counters must be provided to indicate when the test is finished so that the signature analyzers may be stopped so that the signature is frozen and the value held by the signature analyzer is independent of the number of clock cycles applied. Any attempt to use the current art type of structure to accomplish a complete all encompassing scan based self-test just adds more logic and complexity. All of the advances to this kind of methodology cost more circuit area and impacts functional performance which is not acceptable to modern design goals.